Modern memory, such as dynamic random access memory (DRAM), is used throughout the computer industry. Memory is organized into pages. Each page of memory contains data for a number of contiguous memory locations. Memory devices, such as DRAM, are further organized into a small number of banks per DRAM device (e.g., four banks). Each of these devices has many pages per bank. Only a single page can be accessed from a bank at a time.
Before a particular page within a bank can be accessed, that page must be opened using an “activate” command. This activate command is also known as a row command. A memory request requiring a page to be opened is called a “page empty” access request. A memory request to a page that has already been opened is known as a “page hit” access request. A page may be closed using a “pre-charge” command. If page P0 is open when a request is received to access a location in page P1 that happens to be located in the same memory bank as P0, page P0 must first be closed before page P1 can be opened. A page conflict, such as this, occurs when one page must be closed before a desired page can be opened. This situation is known as a “page miss” access. Page miss has a larger access latency than a page empty and a page empty has a larger access latency than a page hit.
Page hit and page empty accesses to different memory banks may be interleaved such that available data bandwidth may be maintained. Page miss accesses, however, typically result in a reduction of available data bandwidth. Therefore, page misses are particularly detrimental for DRAM performance.
Memory performance is partly limited by poor command and data bus bandwidth utilization that occurs with DRAM page misses when requests are sequentially scheduled. Conventional overlapped scheduling techniques attempt to overlap the pre-charge/activate phases of adjacent commands to reduce the page miss/empty penalty while maintaining the order in which the CAS for these adjacent commands are issued to be the same as in order execution.